Semiconductor device

ABSTRACT

In a semiconductor device of the present invention, a clock is not changed instantaneously but it is changed over maximum N+1/M clocks (N: integer not less than 2) by shifting delay cells in a step by step manner to make the phase state of a previous reference signal and the phase state of a present reference signal coincide with each other, whereby the clock is synchronized with the reference signal with accuracy, and the duty of the output clock is kept constant. With this semiconductor device, it is possible to prevent the duty of the clock from being discontinuous when a signal whose reference signal does not coincide with the clock is inputted and reset is made to a rising edge of this reference signal.

TECHNICAL FIELD

The present invention relates to a semiconductor device forsynchronizing a clock signal with a reference signal such as ahorizontal sync signal in a video signal.

BACKGROUND ART

In recent years, digitization of video signal processing has beenadvanced, and a semiconductor device which performs video signalprocessing using a clock synchronized with a reference signal such as ahorizontal sync signal has been utilized. As an example, there is asemiconductor device disclosed in Japanese Published Patent ApplicationNo. 2002-290218.

FIG. 21 shows a configuration example of such conventional semiconductordevice.

A conventional semiconductor device shown in FIG. 21( a) includes aclock input terminal 101, delay cells 102 to 105, a phase comparator106, a controller 107, a reference signal input terminal 108, a selector109, and a sync clock output terminal 110.

The delay cells 102 to 105 shift the phase of a clock inputted to theclock input terminal 101, each by 1/4 clock.

The phase comparator 106 compares the phase of a clock that is one clockafter the input clock with the phase of the output clock of the delaycell 105.

The controller 107 controls the delay values of the delay cells 102 to105 on the basis of the output of the phase comparator 106.

The selector 109 selects, as a sync clock, a clock whose phase isclosest to the phase of the reference signal inputted to the referencesignal input terminal 108 from among the clocks outputted from therespective delay cells 102 to 105, and outputs the sync clock throughthe sync clock output terminal 110 to the outside.

A description will be given of the operation of the conventionalsemiconductor device constructed as described above, with reference toFIG. 21( b).

A clock inputted to the clock input terminal 101 is delayed by the fourstages of delay cells 102 to 105. Then, in the phase comparator 106, thephase of a clock that is one clock after the clock inputted to the clockinput terminal 101 is compared with the phase of the clock outputtedfrom the delay cell 105, and the delay values of the respective delaycells 102 to 105 are controlled by the controller 107 on the basis of aphase difference that is detected as a result of the comparison.

The selector 109 selects an edge clock which is a rear part of thereference signal and is closest to the phase of the reference signal,from among the delay clocks outputted from the respective delay cells102 to 105. In this example, the clock outputted from the delay cell 103is selected as a sync clock, and the sync signal is outputted throughthe sync clock output terminal 110.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention

However, in the case of a signal having a reference signal that is notsynchronized with a clock, such as an analog H pulse, when reset is madeto a rising edge of the reference signal, a clock whose phase is closestto the edge of the reset signal is selected instantaneously, whereby aposition where the duty of the clock becomes discontinuous exists.Further, if the subsequent signal processing is carried out with theclock duty having the discontinuous portion, a signal might be droppedout during arithmetic operation, and thereby the timing constraintbetween the data and the clock cannot be satisfied.

The present invention is made to solve the above-described problems andhas for its object to provide a semiconductor device which canaccurately synchronize a clock with a reference signal, and can keep theduty of an outputted sync signal constant.

MEANS TO SOLVE THE PROBLEMS

In order to solve the above-mentioned problems, according to a firstaspect of the present invention, there is provided a semiconductordevice for phase-shifting an input clock using N stages of delay cells,each delaying the clock by 1/N of the period of the clock, selecting aclock which is most synchronized with a reference signal from amongclocks outputted from the respective delay cells using a selector, andoutputting the selected clock as a sync clock, and the semiconductordevice comprises: a reference signal phase detection circuit fordetecting phase states of a present reference signal and a previousreference signal on the basis of phase differences between the clockswhich have been phase-shifted each by 1/N period and the presentreference signal, and phase differences between the 1/N periodphase-shifted clocks and the previous reference signal that is one lineprevious to the present reference signal; a comparison circuit forcomparing the phase states of the present reference signal and theprevious reference signal which are detected by the reference signalphase detection circuit; a phase control circuit for shifting the phasestate of the present reference signal to make it coincide with the phasestate of the previous reference signal, when the comparison circuitdetects that the phase states of the present reference signal and theprevious reference signal do not coincide with each other; and aselector control circuit for controlling the selector on the basis ofthe output of the phase control circuit.

Therefore, the duty of the outputted sync clock can always be keptconstant. As a result, it is possible to significantly reduce the timingconstraint at an interface with a subsequent LSI, and prevent missing ofsignals during calculation in signal processing, resulting in satisfiedtiming constraint between data and clocks.

According to a second aspect of the present invention, in thesemiconductor device defined in the first aspect, the phase controlcircuit performs the phase control by counting up the number of clocksfor each step.

Therefore, when the phase of the present reference signal is delayed incomparison with that of the previous reference signal, since the phaseof the present reference signal can be made to coincide with the phaseof the previous reference signal by advancing it in a stepwise manner, async clock can be selectively outputted using the phase-controlledreference signals, thereby the duty of the sync clock can always be keptconstant.

According to a third aspect of the present invention, in thesemiconductor device defined in the first aspect, the phase controlcircuit performs the phase control by counting down the number of clocksfor each step.

Therefore, when the phase of the present reference signal is advanced incomparison with that of the previous reference signal, since the phaseof the present reference signal can be made to coincide with the phaseof the previous reference signal by delaying it in a stepwise manner, async clock can be selectively outputted using the phase-controlledreference signals, thereby the duty of the sync clock can always be keptconstant.

According to a fourth aspect of the present invention, in thesemiconductor device defined in the first aspect, the phase controlcircuit shifts the phase of the clock of the present reference signal ata clock rate interval equivalent to a (1+N)/N clock so as to bring thephase of the present reference signal close to the phase of the previousreference signal.

Therefore, when the phases of the present reference signal and theprevious reference signal do not coincide with each other, since thephase of the present reference signal can be made to coincide with thephase of the previous reference signal by shifting the phase of theclock of the present reference signal in a stepwise manner, the duty ofthe sync clock can always be kept constant.

According to a fifth aspect of the present invention, in thesemiconductor device defined in the first aspect, the phase controlcircuit shifts the phase of the clock of the present reference signal ata clock rate interval equivalent to a (N−1)/N clock so as to bring thephase of the present reference signal close to the phase of the previousreference signal.

Therefore, when the phases of the present reference signal and theprevious reference signal do not coincide with each other, since thephase of the present reference signal can be made to coincide with thephase of the previous reference signal by shifting the phase of theclock of the present reference signal in a stepwise manner, the duty ofthe sync clock can always be kept constant.

According to a sixth aspect of the present invention, in thesemiconductor device defined in the first aspect, the phase controlcircuit shifts the phase of the clock of the present reference signal sothat the clock rate interval becomes equal to or larger than one clockto bring the phase of the present reference signal close to the phase ofthe previous reference signal.

Therefore, when the phases of the present reference signal and theprevious reference signal do not coincide with each other, since thephase of the present reference signal can be made to coincide with thephase of the previous reference signal by shifting the phase of theclock of the present reference signal in a stepwise manner, the duty ofthe sync clock can always be kept constant.

According to a seventh aspect of the present invention, in thesemiconductor device defined in the first aspect, the phase controlcircuit shifts the phase of the clock of the present reference signal sothat the clock rate interval becomes equal to or smaller than one clockto bring the phase of the present reference signal close to the phase ofthe previous reference signal.

Therefore, when the phases of the present reference signal and theprevious reference signal do not coincide with each other, since thephase of the present reference signal can be made to coincide with thephase of the previous reference signal by shifting the phase of theclock of the present reference signal in a stepwise manner, the duty ofthe sync clock can always be kept constant.

According to an eighth aspect of the present invention, in thesemiconductor device defined in any of the first to seventh aspects, thephase control circuit counts the number of clocks clock by clock, andperforms the phase control on the basis of the count value.

Therefore, the phase of the clock of the present reference signal can becontrolled in units of clocks.

According to a ninth aspect of the present invention, in thesemiconductor device defined in any of the first to seventh aspects, thephase control circuit counts the number of clocks in units of 1/M-lines(M: integer not less than 2), and performs the phase control on thebasis of the count value.

Therefore, the phase of the clock of the present reference signal can becontrolled in units of 1/M-lines.

According to a tenth aspect of the present invention, in thesemiconductor device defined in any of the first to seventh aspects, thephase control circuit counts the number of clocks line by line, andperforms the phase control on the basis of the count value.

Therefore, the phase of the clock of the present reference signal can becontrolled in units of lines.

EFFECTS OF THE INVENTION

According to the semiconductor device of the present invention, apredetermined initial value is outputted as a quantization factor untilthe PLL is locked. When a signal that is not synchronized with theclock, e.g., an analog H pulse, is reset, the phase of the clock of thepresent reference signal is shifted to make it coincide with the phasestate of the previous reference signal while securing the clock dutywidth. Therefore, the duty of the outputted sync clock can always bekept constant, whereby the timing constraint at an interface with asubsequent LSI can be significantly reduced, omission of signals duringcalculations in signal processing is avoided, and the timing constraintcan be satisfied between data and clocks.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating the construction of a semiconductordevice according to a first embodiment of the present invention.

FIG. 2( a) is a diagram illustrating examples of phase states of apresent reference signal and a previous reference signal in thesemiconductor device according to the first embodiment, and FIG. 2( b)is a diagram for explaining a method for performing phase control of thepresent reference signal shown in FIG. 2( a).

FIG. 3( a) is a diagram illustrating examples of phase states of apresent reference signal and a previous reference signal in thesemiconductor device according to the first embodiment, and FIG. 3( b)is a diagram for explaining a method for performing phase control of thepresent reference signal shown in FIG. 3( a).

FIG. 4 is a block diagram illustrating the construction of asemiconductor device according to a second embodiment of the presentinvention.

FIG. 5( a) is a diagram illustrating examples of phase states of apresent reference signal and a previous reference signal in thesemiconductor device according to the second embodiment, and FIG. 5( b)is a diagram for explaining a method for performing phase control of thepresent reference signal shown in FIG. 5( a).

FIG. 6( a) is a diagram illustrating examples of phase states of apresent reference signal and a previous reference signal in thesemiconductor device according to the second embodiment, and FIG. 6( b)is a diagram for explaining a method for performing phase control of thepresent reference signal shown in FIG. 6( a).

FIG. 7 is a block diagram illustrating the construction of asemiconductor device according to a third embodiment of the presentinvention.

FIG. 8( a) is a diagram illustrating examples of phase states of apresent reference signal and a previous reference signal in thesemiconductor device according to the third embodiment, and FIG. 8( b)is a diagram for explaining a method for performing phase control of thepresent reference signal shown in FIG. 8( a).

FIG. 9( a) is a diagram illustrating examples of phase states of apresent reference signal and a previous reference signal in thesemiconductor device according to the third embodiment, and FIG. 9( b)is a diagram for explaining a method for performing phase control of thepresent reference signal shown in FIG. 9( a).

FIG. 10 is a block diagram illustrating the construction of asemiconductor device according to a fourth embodiment of the presentinvention.

FIG. 11( a) is a diagram illustrating examples of phase states of apresent reference signal and a previous reference signal in thesemiconductor device according to the fourth embodiment, and FIG. 11( b)is a diagram for explaining a method for performing phase control of thepresent reference signal shown in FIG. 11( a).

FIG. 12( a) is a diagram illustrating examples of phase states of apresent reference signal and a previous reference signal in thesemiconductor device according to the fourth embodiment, and FIG. 12( b)is a diagram for explaining a method for performing phase control of thepresent reference signal shown in FIG. 12( a).

FIG. 13 is a block diagram illustrating the construction of asemiconductor device according to a fifth embodiment of the presentinvention.

FIG. 14( a) is a diagram illustrating examples of phase states of apresent reference signal and a previous reference signal in thesemiconductor device according to the fifth embodiment, and FIG. 14( b)is a diagram for explaining a method for performing phase control of thepresent reference signal shown in FIG. 14( a).

FIG. 15( a) is a diagram illustrating examples of phase states of apresent reference signal and a previous reference signal in thesemiconductor device according to the fifth embodiment, and FIG. 15( b)is a diagram for explaining a method for performing phase control of thepresent reference signal shown in FIG. 15( a).

FIG. 16 is a block diagram illustrating the construction of asemiconductor device according to a sixth embodiment of the presentinvention.

FIG. 17( a) is a diagram illustrating examples of phase states of apresent reference signal and a previous reference signal in thesemiconductor device according to the sixth embodiment, and FIG. 17( b)is a diagram for explaining a method for performing phase control of thepresent reference signal shown in FIG. 17( a).

FIG. 18( a) is a diagram illustrating examples of phase states of apresent reference signal and a previous reference signal in thesemiconductor device according to the sixth embodiment, and FIG. 18( b)is a diagram for explaining a method for performing phase control of thepresent reference signal shown in FIG. 18( a).

FIG. 19 is a diagram illustrating a modification of a semiconductordevice according to the present invention.

FIG. 20 is a diagram illustrating the detailed constructions of acomparison circuit and a phase control circuit as components of thesemiconductor device according to the present invention.

FIG. 21( a) is a diagram illustrating the construction of a conventionalsemiconductor device, and FIG. 21( b) is a diagram for explaining theoperation of the conventional semiconductor device.

DESCRIPTION OF REFERENCE NUMERALS

-   1 . . . clock input terminal-   2˜5 . . . delay cells-   6 . . . phase comparator-   7 . . . controller-   8 . . . previous reference signal input terminal-   9 . . . present reference signal input terminal-   10 . . . reference signal phase detection circuit-   11 . . . comparison circuit-   12 . . . phase control circuit-   13 . . . selector control circuit-   14 . . . selector-   15 . . . sync clock output terminal-   16 . . . phase control circuit-   17 . . . one-line width equal division counter circuit-   18 . . . line counter circuit-   19 . . . switching means-   20 . . . subtracter-   21 . . . selector-   22 . . . selector-   23 . . . adder-   24 . . . selector-   25 . . . flip-flop-   26 . . . EX-OR circuit

BEST MODE TO EXECUTE THE INVENTION

Hereinafter, embodiments of the present invention will be described withreference to the drawings. The embodiments described hereinafter aremerely examples, and the present invention is not restricted thereto.

Embodiment 1

FIG. 1 is a block diagram illustrating the construction of asemiconductor device according to a first embodiment of the presentinvention.

The semiconductor device according to the first embodiment comprises aclock input terminal 1, delay cells 2 to 5, a phase comparator 6, acontroller 7, a previous reference signal input terminal 8, a presentreference signal input terminal 9, a reference signal phase detectioncircuit 10, a comparison circuit 11, a phase control circuit 12, aselector control circuit 13, a selector 14, and a sync clock outputterminal 15.

The delay cells 2 to 5 phase-shift a clock inputted to the clock inputterminal 1, each by 1/4 a period of the clock.

The phase comparator 6 compares the phase of a clock that is one clockafter the clock inputted from the clock input terminal with the phase ofthe output clock of the delay cell 5.

The controller 7 controls the delay values of the delay cells 2 to 5 onthe basis of the output of the phase comparator 6.

The previous reference signal input terminal 8 receives a previousreference signal that is a signal one line prior to a present referencesignal.

The present reference signal input terminal 9 receives the presentreference signal.

The reference signal phase detection circuit 10 detects the phase statesof the previous reference signal and the present reference signal on thebasis of phase differences between the output clocks of the respectivedelay cells 2 to 5 and the previous reference signal that is inputtedthrough the previous reference signal input terminal 8, and the phasedifferences between the output clocks of the respective delay cells 2 to5 and the present reference signal that is inputted through the presentreference signal input terminal 9.

The comparison circuit 11 checks whether the phase states of the presentreference signal and the previous reference signal, which are detectedby the reference signal phase detection circuit 10, coincide with eachother or not.

When the phase states of the present reference signal and the previousreference signal do not coincide with each other, the phase controlcircuit 12 counts up the number of clocks on a step-by-step basis,thereby to shift the phase state of the clock of the present referencesignal at a (1+N)/N clock rate interval (N: integer determined by thestage number of delay cells) to bring the phase state of the presentreference signal close to the phase state of the previous referencesignal. In this first embodiment, the phase control circuit 12 performscount-up on a clock-by-clock basis, and performs phase control at a 5/4clock rate interval.

The selector control circuit 13 controls the selector 14 on the basis ofthe output of the phase control circuit 12.

The selector 14 is controlled by the selector control circuit 13 so asto select one from among the delay cells 2 to 5 as a sync clock, andoutputs the selected clock through the sync clock output terminal 15 tothe outside.

Next, examples of constructions of the comparison circuit 11 and thephase control circuit 12 are shown in FIG. 20.

The comparison circuit 11 includes a subtracter 20, judges as to whichof the phase state 8 s of the previous reference signal and the phasestate 9 s of the present reference signal is larger, and outputs a carrysignal 20 s on the basis of the result of judgement. This signal 20 sindicates 1 when the phase state 8 s of the previous reference signal islarger than the phase state 9 s of the present reference signal, andindicates 0 when the phase state 8 s of the previous reference signal issmaller than the phase state 9 s of the present reference signal.

The phase control circuit 12 includes selectors 21 and 22, an adder 23,a selector 24, a flip-flop (FF) 25, and an EX-OR circuit 26, andperforms phase control by an up-counting operation when the carry signal20 s is 1 while performs phase control by a down-counting operation whenthe carry signal 20 s is 0.

The selector 21 outputs 1 when the carry signal 20 s is 1, and outputs 0when the carry signal 20 s is 0.

The selector 22 outputs 0 when the carry signal 20 s is 1, and outputs 1when the carry signal 20 s is 0.

The adder 23 adds the output 21 s of the selector 21, the output 22 s ofthe selector 22, and the output 25 s of the flip-flop 25.

When the output 26 s of the EX-OR circuit 26 is 1, the selector 24selects the output 23 s of the adder 23 and outputs it to the flip-flop25. When the output 26 s of the EX-OR circuit 26 is 0, since the output25 s of the flip-flop 25 coincides with the previous reference signal,the data is held.

The flip-flop 25 is a flip-flop with an asynchronous reset, and outputs0 when reset is made.

The EX-OR circuit 26 compares the output 25 s of the flip-flop 25 withthe previous reference signal, and outputs 0 when there is a match, andoutputs 1 when there is no match. In the subsequent selector controlcircuit 13, the selector circuit 14 is controlled at a timing when theoutput 26 s of the EX-OR circuit 26 changes from 1 to 0.

The operation of the semiconductor device constructed as described abovewill be described.

Initially, a clock of the same frequency as that of a clock to besynchronized is input to the clock input terminal 1. The inputted clockis delayed by the delay cells 2 to 5, and the output clock of the delaycell 5 is input to the phase comparator 6 as a comparison signal.Further, the clock supplied from the clock input terminal 1 is input tothe phase comparator 6 as a signal to be compared.

In the phase comparator 6, the phase of the output clock of the delaycell 5 is compared with the phase of the clock that is one clock afterthe clock inputted from the clock input terminal 1, and a phasedifference output signal is outputted to the controller 7 when a phasedifference is detected.

In the controller 7, the phase difference output signal is convertedinto a control value for controlling the delay values of the delay cells2 to 5, thereby varying the delay values of the delay cells 2 to 5.

Thereafter, the phase comparator 6 compares the phase of the outputclock of the delay cell 5 with the phase of the clock that is one clockafter the clock inputted from the input terminal 1. This operation isrepeated until the phase comparator 6 comes to detect no phasedifference, and then there is no difference between the phase of theoutput clock of the delay cell 5 and the phase of the clock that is oneclock after the clock inputted from the input terminal 1, i.e., thedelays of the delay cells become approximately equal to each other. Thatis, a 1/4-clock phase-shifted clock is generated at the output of eachdelay cell. Accordingly, a 1/4-clock delayed clock is generated at theoutput of the delay cell 2, a 2/4-clock delayed clock is generated atthe output of the delay cell 3, a 3/4-clock delayed clock is generatedat the output of the delay cell 4, and a 1-clock delayed clock isgenerated at the output of the delay cell 5.

Next, a description will be given of a phase control method for apresent reference signal by the semiconductor device according to thefirst embodiment of the present invention.

In the reference signal phase detection circuit 10, the phase states ofthe previous reference signal and the present reference signal aredetected on the basis of the phase differences between the output clocksof the respective delay cells 2 to 5 and the reference signal, and thephase differences between the output clocks of the respective delaycells 2 to 5 and the present reference signal. The phase state 0 meansthat the phase state of the previous reference signal or the presentreference signal is the same as the phase state of the output of thedelay cell 2, and the count value by the phase control circuit 12 is 0.The phase state 1 means that the phase state of the previous referencesignal or the present reference signal is the same as the phase state ofthe output of the delay cell 3, and the count value by the phase controlcircuit 12 is 1. The phase state 2 means that the phase state of theprevious reference signal or the present reference signal is the same asthe phase state of the output of the delay cell 4, and the count valueby the phase control circuit 12 is 2. The phase state 3 means that thephase state of the previous reference signal or the present referencesignal is the same as the phase state of the output of the delay cell 5,and the count value by the phase control circuit 12 is 3.

Based on the result of the above-mentioned detection, when the phasestate of the previous reference signal is 2 and the phase state of thepresent reference signal is 0 as shown in FIG. 2( a), the phase controlcircuit 12 counts up the number of clocks clock by clock to shift thephase of the clock of the present reference signal at a 5/4 clock rateinterval to bring the phase of the present reference signal close to thephase of the previous reference signal. That is, as shown in FIG. 2( b),the clock edge of the phase state 0 of the present reference signal isphase-shifted 5/4-clock by 5/4-clock to change the clock edge of thepresent reference signal to the clock edge of the phase state 1 and tothe clock edge of the phase state 2, successively, whereby the phasestate of the present reference signal is brought close to the phasestate of the previous reference signal.

Then, the selector control circuit 13 controls the selector 14 on thebasis of the output of the phase control circuit 12, whereby one of theoutput clocks of the delay cells 2 to 5 is selectively outputted as async clock. The sync clock is outputted at a 5/4 clock rate intervalduring the phase control, while it is outputted at a 1 clock rateinterval after the phases of the previous reference signal and thepresent reference signal coincide each other, i.e., after the phasecontrol is completed.

Based on the result of the above-mentioned detection, when the phasestate of the previous reference signal is 0 and the phase state of thepresent reference signal is 2 as shown in FIG. 3( a), the phase controlcircuit 12 phase-shifts the clock edge of the phase state 2 of thepresent reference signal 5/4-clock by 5/4-clock as shown in FIG. 3( b)to change the clock edge of the present reference signal to the clockedge of the phase state 3 and to the clock edge of the phase state 0,successively, whereby the phase state of the present reference signal isbrought close to the phase state of the previous reference signal.

Then, the selector control circuit 13 controls the selector 14 on thebasis of the output of the phase control circuit 12, whereby one of theoutput clocks of the delay cells 2 to 5 is selectively outputted as async clock. The sync clock is outputted at a 5/4 clock rate intervalduring the phase control, and it is outputted at a 1 clock rate intervalafter the phases of the previous reference signal and the presentreference signal coincide, i.e., after the phase control is completed.

In the first embodiment, the semiconductor device is provided with thephase control circuit 12 which performs phase control by counting up thenumber of clocks clock by clock to bring the phase state of the presentreference signal close to the phase state of the previous referencesignal, and the phase of the clock of the present reference signal isshifted at a 5/4 clock rate interval to make it coincide with the phaseof the present reference signal when the signal that is not synchronizedwith the input clock, e.g., the analog H pulse, is reset. Therefore, theduty of the outputted sync clock can be kept constant, whereby thetiming restriction at the interface with the subsequent LSI issignificantly reduced, and the timing restriction between the data andthe clock can be satisfied without losing signals during calculations insignal processing, and eventually, malfunction during signal processingcan be avoided.

While in this first embodiment the phase control circuit 12 performsphase control at a (1+N)/N clock rate interval, the same effects asmentioned above can be obtained even when the clock rate interval isequal to or larger than one clock.

Embodiment 2

FIG. 4 is a block diagram illustrating the construction of asemiconductor device according to a second embodiment of the presentinvention. In FIG. 4, the same reference numerals as those shown in FIG.1 denote the same or corresponding components, and therefore, repeateddescription is not necessary.

The semiconductor device according to the second embodiment is providedwith a phase control circuit 16 that performs phase control by countingdown the number of clocks in a stepwise manner, instead of the phasecontrol circuit 12 that performs phase control by counting up the numberof clocks in a stepwise manner. When the phase states of the presentreference signal and the previous reference signal do not coincide witheach other, the phase control circuit 16 counts down the number ofclocks in a stepwise manner to shift the phase state of the clock of thepresent reference signal with a (N−1)/N clock rate width so as to bringthe phase state of the present reference signal close to the phase stateof the previous reference signal. In this second embodiment, it isassumed that the phase control circuit 16 counts down the number ofclocks on a clock-by-clock basis to perform phase control at a 3/4 clockrate interval.

Next, a description will be given of a phase control method for thepresent reference signal in the semiconductor device according to thesecond embodiment.

In the reference signal phase detection circuit 10, the phase states ofthe previous reference signal and the present reference signal aredetected on the basis of the phase differences between the output clocksof the respective delay cells 2 to 5 and the previous reference signal,and the phase differences between the output clocks of the respectivedelay cells 2 to 5 and the present reference signal.

Based on the result of the detection, when the phase state of theprevious reference signal is 0 and the phase state of the presentreference signal is 2 as shown in FIG. 5( a), the phase control circuit16 counts down the number of clocks clock by clock to bring the phase ofthe clock of the present reference signal close to the phase of theprevious reference signal at a 3/4 clock rate interval. That is, asshown in FIG. 5( b), the clock edge of the present reference signal inthe phase state 2 is phase-shifted 3/4-clock by 3/4-clock to change theclock edge of the present reference signal to the clock edge in thephase state 1 and to the clock edge in the phase state 0, successively,so as to bring the phase state of the present reference signal close tothat of the previous reference signal.

Then, the selector control circuit 13 controls the selector 14 on thebasis of the output of the phase control circuit 16, whereby one of theoutput clocks of the delay cells 2 to 5 is selectively outputted as async clock. The sync clock is outputted at a 3/4 clock rate intervalduring the phase control, and it is outputted at a 1 clock rate intervalafter the phases of the previous reference signal and the presentreference signal coincide with each other, i.e., after the phase controlis completed.

Based on the result of the detection, when the phase state of theprevious reference signal is 2 and the phase state of the presentreference signal is 0 as shown in FIG. 6( a), the phase control circuit12 phase-shifts the clock edge of the present reference signal in thephase state 0 3/4-clock by 3/4-clock as shown in FIG. 6( b) to changethe clock edge of the present reference signal to the clock edge in thephase state 3 and to the clock edge in the phase state 2, successively,thereby bringing the phase state of the present reference signal closeto that of the previous reference signal.

Then, the selector control circuit 13 controls the selector 14 on thebasis of the output of the phase control circuit 16, whereby one of theoutput clocks of the delay cells 2 to 5 is selectively outputted as async clock. The sync clock is outputted at a 3/4 clock rate intervalduring the phase control, and it is outputted at a 1 clock rate intervalafter the phases of the previous reference signal and the presentreference signal coincide, i.e., after the phase control is completed.

According to the second embodiment, the semiconductor device is providedwith the phase control circuit 16 which performs phase control bycounting down the number of clocks clock by clock so as to bring thephase state of the present reference signal close to the phase state ofthe previous reference signal, and the phase of the clock of the presentreference signal is shifted at a 3/4 clock rate interval to make itcoincide with the phase of the previous reference signal when the signalthat is not synchronized with the clock is reset. Therefore, the duty ofthe output sync clock can always be kept constant, whereby the timingconstraint at an interface with a subsequent LSI can be significantlyreduced, and omission of signals during calculations in signalprocessing is avoided, and consequently, the timing constraint can besatisfied between data and clocks.

While in this second embodiment the phase control circuit 16phase-shifts the clock at a (N−1)/N clock rate interval, the sameeffects as mentioned above can be achieved so long as the clock rateinterval is one clock or shorter.

Embodiment 3

FIG. 7 is a block diagram illustrating the construction of asemiconductor device according to a third embodiment of the presentinvention. In FIG. 7, the same reference numerals as those shown in FIG.1 denote the same or corresponding components and, therefore, repeateddescription is not necessary.

The semiconductor device according to the third embodiment is providedwith a one-line width equal division counter circuit 17 in addition tothe components of the semiconductor device according to the firstembodiment.

The one-line width equal division counter circuit 17 equally divides theline width by the number of clocks per line M (M: integer not less than2), and controls the phase control circuit 12 so as to count the numberof clocks in line units (1/M-line units) into which the line width isequally divided.

Next, a description will be given of a phase control method for thereference signal in the semiconductor device according to the thirdembodiment.

In the reference signal phase detection circuit 10, the phase states ofthe previous reference signal and the present reference signal aredetected on the basis of the phase differences between the output clocksof the respective delay cells 2 to 5 and the previous reference signal,and the phase differences between the output clocks of the respectivedelay cells 2 to 5 and the present reference signal.

Based on the result of the detection, when the phase state of theprevious reference signal is 2 and the phase state of the presentreference signal is 0 as shown in FIG. 8( a), the phase control circuit16 counts up the number of clocks in units of 1/M-lines to bring thephase of the clock of the present reference signal close to the phase ofthe previous reference signal at a 5/4 clock rate interval. That is, asshown in FIG. 8( b), the clock edge of the present reference signal inthe phase state 0 is phase-shifted 5/4-clock by 5/4-clock to change theclock edge of the present reference signal to the clock edge in thephase state 1 and to the clock edge in the phase state 2, successively,thereby bringing the phase state of the present reference signal closeto that of the previous reference signal.

Then, the selector control circuit 13 controls the selector 14 on thebasis of the output of the phase control circuit 12, whereby one of theoutput clocks of the delay cells 2 to 5 is selectively outputted as async clock. The sync clock is outputted at a 5/4 clock rate intervalduring the phase control of the clock of the present reference signal,and it is outputted at a 1 clock rate interval after the phases of theprevious reference signal and the present reference signal coincide witheach other, i.e., after the phase control is completed.

Based on the result of the detection, when the phase state of theprevious reference signal is 0 and the phase state of the presentreference signal is 2 as shown in FIG. 9( a), the phase control circuit12 phase-shifts the clock edge of the present reference signal in thephase state 2 5/4-clock by 5/4-clock as shown in FIG. 9( b) to changethe clock edge of the present reference signal to the clock edge in thephase state 3 and to the clock edge of the phase state 0, successively,thereby bringing the phase of the present reference signal close to thephase state of the previous reference signal.

Then, the selector control circuit 13 controls the selector 14 on thebasis of the output of the phase control circuit 12, whereby one of theoutput clocks of the delay cells 2 to 5 is selectively outputted as async clock. The sync clock is outputted at a 5/4 clock rate intervalduring the phase control for the present reference signal, and it isoutputted at a 1 clock rate interval after the phases of the previousreference signal and the present reference signal coincide, i.e., afterthe phase control is completed.

According to the third embodiment, the semiconductor device is providedwith the phase control circuit 12 which performs phase control bycounting up the number of clocks in units of 1/M-lines so as to bringthe phase state of the present reference signal close to the phase stateof the previous reference signal, and the phase of the clock of thepresent reference signal is shifted at a 5/4 clock rate interval to makeit coincide with the phase of the previous reference signal when thesignal that is not synchronized with the clock is reset. Therefore, theduty of the output sync clock can always be kept constant, whereby thetiming constraint at an interface with a subsequent LSI can besignificantly reduced, and omission of signals during calculations insignal processing is avoided, and consequently, the timing constraintcan be satisfied between data and clocks.

Embodiment 4

FIG. 10 is a block diagram illustrating the construction of asemiconductor device according to a fourth embodiment of the presentinvention. In FIG. 10, the same reference numerals as those shown inFIG. 1 denote the same or corresponding components and, therefore,repeated description is not necessary.

The semiconductor device according to the fourth embodiment is providedwith a one-line width equal division counter circuit 17 in addition tothe components of the semiconductor device according to the secondembodiment.

The one-line width equal division counter circuit 17 equally divides theline width by the number of clocks per line M (M: integer not less than2), and controls the phase control circuit 16 so as to count the numberof clocks in line units (1/M-line units) into which the line width isequally divided.

Next, a description will be given of a phase control method for thereference signal in the semiconductor device according to the fourthembodiment.

In the reference signal phase detection circuit 10, the phase states ofthe previous reference signal and the present reference signal aredetected on the basis of the phase differences between the output clocksof the respective delay cells 2 to 5 and the previous reference signal,and the phase differences between the output clocks of the respectivedelay cells 2 to 5 and the present reference signal.

Based on the result of the detection, when the phase state of theprevious reference signal is 0 and the phase state of the presentreference signal is 2 as shown in FIG. 11( a), the phase control circuit16 counts down the number of clocks in units of 1/M-lines to bring thephase of the clock of the present reference signal close to the phase ofthe previous reference signal at a 3/4 clock rate interval. That is, asshown in FIG. 11( b), the number of clocks is counted down in units of1/M-lines to change the clock edge of the present reference signal inthe phase state 2 to the clock edge in the phase state 1 and to theclock edge in the phase state 0, successively, thereby bringing thephase state of the present reference signal close to that of theprevious reference signal.

Then, the selector control circuit 13 controls the selector 14 on thebasis of the output of the phase control circuit 16, whereby one of theoutput clocks of the delay cells 2 to 5 is selectively outputted as async clock. The sync clock is outputted at a 3/4 clock rate intervalduring the phase control for the clock of the present reference signal,and it is outputted at a 1 clock rate interval after the phases of theprevious reference signal and the present reference signal coincide witheach other, i.e., after the phase control is completed.

Based on the result of the detection, when the phase state of theprevious reference signal is 2 and the phase state of the presentreference signal is 0 as shown in FIG. 12( a), the phase control circuit16 phase-shifts the clock edge of the present reference signal in thephase state 0 3/4-clock by 3/4-clock as shown in FIG. 12( b) to changethe clock edge of the present reference signal to the clock edge in thephase state 3 and to the clock edge of the phase state 2, successively,thereby bringing the phase of the present reference signal close to thephase state of the previous reference signal.

Then, the selector control circuit 13 controls the selector 14 on thebasis of the output of the phase control circuit 16, whereby one of theoutput clocks of the delay cells 2 to 5 is selectively outputted as async clock. The sync clock is outputted at a 3/4 clock rate intervalduring the phase control, and it is outputted at a 1 clock rate intervalafter the phases of the previous reference signal and the presentreference signal coincide with each other, i.e., after the phase controlis completed.

According to the fourth embodiment, the semiconductor device is providedwith the phase control circuit 16 which performs phase control bycounting down the number of clocks in units of 1/M-lines so as to bringthe phase state of the present reference signal close to the phase stateof the previous reference signal, and the phase of the clock of thepresent reference signal is shifted at a 3/4 clock rate interval to makeit coincide with the phase of the previous reference signal when thesignal that is not synchronized with the clock, e.g., an analog H pulse,is reset. Therefore, the duty of the output sync clock can always bekept constant, whereby the timing constraint at an interface with asubsequent LSI can be significantly reduced, and omission of signalsduring calculations in signal processing is avoided, and consequently,the timing constraint can be satisfied between data and clocks.

Embodiment 5

FIG. 13 is a block diagram illustrating the construction of asemiconductor device according to a fifth embodiment of the presentinvention. In FIG. 13, the same reference numerals as those shown inFIG. 1 denote the same or corresponding components, and therefore,repeated description is not necessary.

The semiconductor device according to the fifth embodiment is providedwith a line counter circuit 18 in addition to the components of thesemiconductor device according to the first embodiment.

The line counter circuit 18 controls the phase control circuit 12 so asto count the number of clocks line by line.

Next, a description will be given of a phase control method for thepresent reference signal in the semiconductor device according to thefifth embodiment.

In the reference signal phase detection circuit 10, the phase states ofthe previous reference signal and the present reference signal aredetected on the basis of the phase differences between the output clocksof the respective delay cells 2 to 5 and the previous reference signal,and the phase differences between the output clocks of the respectivedelay cells 2 to 5 and the present reference signal.

Based on the result of the detection, when the phase state of theprevious reference signal is 2 and the phase state of the presentreference signal is 0 as shown in FIG. 14( a), the phase control circuit12 counts up the number of clocks line by line to bring the phase of theclock of the present reference signal close to the phase of the previousreference signal at a 5/4 clock rate interval. That is, as shown in FIG.14( b), the clock edge of the present reference signal in the phasestate 0 is phase-shifted 5/4-clock by 5/4-clock to change the clock edgeof the present reference signal to the clock edge in the phase state 1and to the clock edge in the phase state 2, successively, so as to bringthe phase state of the present reference signal close to that of theprevious reference signal.

Then, the selector control circuit 13 controls the selector 14 on thebasis of the output of the phase control circuit 12, whereby one of theoutput clocks of the delay cells 2 to 5 is selectively outputted as async clock. The sync clock is outputted at a 5/4 clock rate intervalduring the phase control, and it is outputted at a 1 clock rate intervalafter the phases of the previous reference signal and the presentreference signal coincide with each other, i.e., after the phase controlis completed.

Based on the result of the detection, when the phase state of theprevious reference signal is 0 and the phase state of the presentreference signal is 2 as shown in FIG. 15( a), the phase control circuit12 phase-shifts the clock edge of the present reference signal in thephase state 2 5/4-clock by 5/4-clock as shown in FIG. 15( b) to changethe clock edge of the present reference signal to the clock edge in thephase state 3 and to the clock edge in the phase state 0, successively,thereby bringing the phase state of the present reference signal closeto that of the previous reference signal.

Then, the selector control circuit 13 controls the selector 14 on thebasis of the output of the phase control circuit 12, whereby one of theoutput clocks of the delay cells 2 to 5 is selectively outputted as async clock. The sync clock is outputted at a 5/4 clock rate intervalduring the phase control, and it is outputted at a 1 clock rate intervalafter the phases of the previous reference signal and the presentreference signal coincide, i.e., after the phase control is completed.

According to the fifth embodiment, the semiconductor device is providedwith the phase control circuit 12 which performs phase control bycounting up the number of clocks line by line so as to bring the phasestate of the present reference signal close to the phase state of theprevious reference signal, and the phase of the clock of the presentreference signal is shifted at a 5/4 clock rate interval to make itcoincide with the phase of the previous reference signal when the signalthat is not synchronized with the clock, e.g., an analog H pulse, isreset. Therefore, the duty of the output sync clock can always be keptconstant, whereby the timing constraint at an interface with asubsequent LSI can be significantly reduced, and omission of signalsduring calculations in signal processing is avoided, and consequently,the timing constraint can be satisfied between data and clocks.

Embodiment 6

FIG. 16 is a block diagram illustrating the construction of asemiconductor device according to a sixth embodiment of the presentinvention. In FIG. 16, the same reference numerals as those shown inFIG. 1 denote the same or corresponding components, and therefore,repeated description is not necessary.

The semiconductor device according to the fifth embodiment is providedwith a line counter circuit 18 in addition to the components of thesemiconductor device according to the second embodiment.

The line counter circuit 18 controls the phase control circuit 12 so asto count the number of clocks line by line.

Next, a description will be given of a phase control method for thepresent reference signal in the semiconductor device according to thesixth embodiment.

In the reference signal phase detection circuit 10, the phase states ofthe previous reference signal and the present reference signal aredetected on the basis of the phase differences between the output clocksof the respective delay cells 2 to 5 and the previous reference signal,and the phase differences between the output clocks of the respectivedelay cells 2 to 5 and the present reference signal.

Based on the result of the detection, when the phase state of theprevious reference signal is 0 and the phase state of the presentreference signal is 2 as shown in FIG. 17( a), the phase control circuit16 counts up the number of clocks line by line to bring the phase of theclock of the present reference signal close to the phase of the previousreference signal at a 3/4 clock rate interval. That is, as shown in FIG.17( b), the clock edge of the present reference signal in the phasestate 2 is phase-shifted 3/4-clock by 3/4-clock to change the clock edgeof the present reference signal to the clock edge in the phase state 1and to the clock edge in the phase state 0, successively, so as to bringthe phase state of the present reference signal close to that of theprevious reference signal.

Then, the selector control circuit 13 controls the selector 14 on thebasis of the output of the phase control circuit 16, whereby one of theoutput clocks of the delay cells 2 to 5 is selectively outputted as async clock. The sync clock is outputted at a 3/4 clock rate intervalduring the phase control, and it is outputted at a 1 clock rate intervalafter the phases of the previous reference signal and the presentreference signal coincide with each other, i.e., after the phase controlis completed.

Based on the result of the detection, when the phase state of theprevious reference signal is 0 and the phase state of the presentreference signal is 2 as shown in FIG. 15( a), the phase control circuit12 phase-shifts the clock edge of the present reference signal in thephase state 2 5/4-clock by 5/4-clock as shown in FIG. 15( b) to changethe clock edge of the present reference signal to the clock edge in thephase state 3 and to the clock edge in the phase state 0, successively,thereby bringing the phase state of the present reference signal closeto that of the previous reference signal.

Then, the selector control circuit 13 controls the selector 14 on thebasis of the output of the phase control circuit 16, whereby one of theoutput clocks of the delay cells 2 to 5 is selectively outputted as async clock. The sync clock is outputted at a 3/4 clock rate intervalduring the phase control, and it is outputted at a 1 clock rate intervalafter the phases of the previous reference signal and the presentreference signal coincide, i.e., after the phase control is completed.

According to the sixth embodiment, the semiconductor device is providedwith the phase control circuit 16 which performs phase control bycounting up the number of clocks line by line so as to bring the phasestate of the present reference signal close to the phase state of theprevious reference signal, and the phase of the clock of the presentreference signal is shifted at a 3/4 clock rate interval to make itcoincide with the phase of the previous reference signal when the signalthat is not synchronized with the clock, e.g., an analog H pulse, isreset. Therefore, the duty of the output sync clock can always be keptconstant, whereby the timing constraint at an interface with asubsequent LSI can be significantly reduced, and omission of signalsduring calculations in signal processing is avoided, and consequently,the timing constraint can be satisfied between data and clocks.

A highly reliable semiconductor device can be realized by combining thefirst to sixth embodiments as desired to perform phase control ofreference signals.

For example, an example of construction of a semiconductor deviceobtained by combining the first embodiment and the fifth embodiment isshown in FIG. 19. The semiconductor device shown in FIG. 19 is providedwith a switching means 19 for controlling the phase control circuit 12to perform counting line by line or clock by clock, in addition to thesemiconductor device according to the first embodiment.

When phase control of reference signals is started using thesemiconductor device thus constructed, the phase control circuit 12 iscontrolled by the switching means 190 to carry out phase control line byline, and the phase state of the present reference signal issuccessively changed by counting up the number of clocks line by line asdescribed for the fifth embodiment to bring the phase state of thepresent reference signal to that of the previous reference signal.

When the phase of the present reference signal gets close to the phaseof the previous reference signal, the phase control circuit 12 iscontrolled by the switching means 19 so as to perform phase controlclock by clock. Then, as described for the first embodiment, the phasestate of the clock of the present reference signal is made to coincidewith the phase state of the previous reference signal while counting upthe number of clocks clock by clock.

As described above, rough phase control is carried out line by line whenphase control is started, and thereafter, phase control is preciselycarried out clock by clock, whereby the phase state of the previousreference signal can be made to coincide with the phase state of thepresent reference signal.

APPLICABILITY IN INDUSTRY

A semiconductor device according to the present invention is useful as asemiconductor device which can keep the duty width of a sync clock to beoutputted constant when synchronizing the clock to a reference signalsuch as an analog H pulse.

1. A semiconductor device comprising: N stages of delay cells, each ofthe N delay cells delaying an input clock signal by 1/N clock period andoutputting the respective delayed clock signal; a reference signal phasedetection circuit for detecting a phase state of a present referencesignal based on phase differences between the clocks outputted from thedelay cells and the present reference signal, and detecting a phasestate of a previous reference signal based on phase differences betweenthe clocks outputted from the delay cells and the previous referencesignal; a comparison circuit for comparing the phase state of thepresent reference signal and the phase state of the previous referencesignal which are detected by the reference signal phase detectioncircuit; a phase control circuit for shifting the phase state of thepresent reference signal to make it coincide with the phase state of theprevious reference signal, when the comparison circuit detects that thephase states of the present reference signal and the previous referencesignal do not coincide with each other; a selector; and a selectorcontrol circuit for controlling the selector based on the output of thephase control circuit to select a clock which is most synchronized withthe shifted phase state of the present reference signal from amongclocks outputted from the respective delay cells, and to output theselected clock as a sync clock.
 2. A semiconductor device as defined inclaim 1 wherein said phase control circuit performs the phase control bycounting up the number of clocks stepwisely.
 3. A semiconductor deviceas defined in claim 1 wherein said phase control circuit performs thephase control by counting down the number of clocks stepwisely.
 4. Asemiconductor device as defined in claim 1 wherein said phase controlcircuit shifts the phase of the clock of the present reference signal ata clock rate interval equivalent to a (1+N)/N clock so as to bring thephase of the present reference signal close to the phase of the previousreference signal.
 5. A semiconductor device as defined in claim 1wherein said phase control circuit shifts the phase of the clock of thepresent reference signal at a clock rate interval equivalent to a(N−1)/N clock so as to bring the phase of the present reference signalclose to the phase of the previous reference signal.
 6. A semiconductordevice as defined in claim 1 wherein said phase control circuit shiftsthe phase of the clock of the present reference signal so that the clockrate interval becomes equal to or larger than one clock to bring thephase of the present reference signal close to the phase of the previousreference signal.
 7. A semiconductor device as defined in claim 1wherein said phase control circuit shifts the phase of the clock of thepresent reference signal so that the clock rate interval becomes equalto or smaller than one clock to bring the phase of the present referencesignal close to the phase of the previous reference signal.
 8. Asemiconductor device as defined in claim 1 wherein said phase controlcircuit counts the number of clocks clock by clock, and performs thephase control on the basis of the count value.
 9. A semiconductor deviceas defined in claim 1 wherein said phase control circuit counts thenumber of clocks in units of 1/M-lines, wherein M is an integer not lessthan 2, and performs the phase control on the basis of the count value.10. A semiconductor device as defined in claim 1 wherein said phasecontrol circuit counts the number of clocks line by line, and performsthe phase control on the basis of the count value.